Zettabolt has been partnering with trail blazers in their respective domains (nVidia, AMD, Tiger Graph, EnnoCAD) to build and deploy cutting edge products in Big Data, Graph and Semiconductor areas.
Innovative use of CPUs, GPUs and FPGAs has helped build solutions which can scale up to TBs of data and provide 100x performance improvements.
WHY PARTNER
WITH ZETTABOLT?
With deep understanding of building and optimizing CPU applications (SIMD, vector processing, NUMA etc.) and offloading critical computations to heterogeneous devices (GPUs, FPGAs), Zettabolt has been able to build solutions which span Big Data (Hadoop, Hive, Spark), Graph Analytics (algorithms, neural networks) and provide significant cost and performance gains for the customers.
Zettabolt has expertise in working with diverse and cross-geography (US, India, Asia-PAC) teams to deliver best possible outcomes for the partners and customers. Our development processes are modelled after best product companies in the world and can be tailored to suit any customizations.
SUCCESS STORY
OUR JOINT GRAPH ACCELERATION SOLUTIONS
Deployed on
multi-node-multi-GPU
compute clusters
100x upwards
performance
gains
PageRank,
Louvain, Jaccard
etc.
Graph sizes of
billions of
vertices & edges
SPARK RAPIDS
Deep understanding of Spark workload optimizations using RAPIDs
Integration of RAPIDs
qualification tool into ZettaProf
Marking out workloads suited for GPU acceleration
SUCCESS STORY
OUR JOINT BIG DATA ACCELERATION SOLUTIONS
Creation of ZettaAccel middleware to offload SQL operations from BigData tools to FPGAs
Hadoop : Offloading sorting and compression to FPGAs
10x faster sorting
2x faster compression
Hive & Spark : Offloading SQL operations to FPGAs
4x faster TPC-H workloads, 40% TCO savings
Multiple TBs and multi-node deployment on cloud as well as on-prem
SUCCESS STORY
OUR JOINT GRAPH & NEURAL NETWORK SOLUTIONS
Creation of ZettaAccel middleware to offload graph algorithms (PageRank, Louvain, Jaccard) from TigerGraph to nVidia GPUs
Solution works for graphs with billions of edges
Supports multi-node-multi GPU compute
100x performance improvements
SUCCESS STORY
OUR JOINT SEMICONDUCTOR SOLUTIONS
Chip design software
RTL/GL sign-off products : Low Power Checker, Power Analysis & Optimization, Design For Testability, Clock/Reset Domain Crossing
Proven for billion transistor designs
Graphical User Interface
Qt based design exploration cockpit Features : Design hierarchy, source code viewer, UPF browser, schematic etc.
